Syed Arsalan Jawed
I have been working on Analog/Mixed-Signal Integrated Circuits design since last 16 years. I graduated from NED UET, Karachi in 2001 and then worked with Avaz Networks, a Silicon-Valley Company on RTL design and verification of a high-density Line Echo Cancellation Engine for a couple of years. Joined Linkoping University, Sweden in 2003 for Masters in SOC, which concluded with a Masters Thesis on Sigma-Delta Modulators with Fraunhofer Institute of Integrated Circuits, Germany in 2005. The same year I joined University of Trento and Fondazione Bruno Kessler, Trento, Italy for my PhD on Readout Interface Design for MEMS Capacitive Microphones. Worked with ST-Microelectronics, Milano and Analog-Devices, Copenhagen as a Guest PhD Student. This Phd results in 20+ publications and 2 patents with 3 successful MEMS Readout ASICs.
After finishing PhD in 2009, worked with Institute of Applied Technologies, Islamabad as Group-Head on the Readout Interface Design for an Opto-Electrical sensor array for IR imaging applications. Successfully taped-out and characterized 3 ASICs for array-sizes as large as 100k-pixels. Also developed automated temperature-controlled characterization setups for these ASICs. In 2012, joined Open-Silicon, a Silicon-Valley company, as Manager of their Analog Group and worked on the IP development for 2.5D IOs and DDR3/4 Combo IOs. In 2014, joined Karachi Institute of Economics and Technology (KIET) and established the Electronic Devices, Circuits and Systems (EDCAS) Resaerch group.
EDCAS has been involved in ASIC and IP development for Sensor Readout Interface, Wireless Power Transfer Circuit, IO Design for Gbps Signaling over Electrical Interconencts, SAR ADCs, Sigma-Delta Modulators, Voltage Reference Circuits, Current Reference Circuits, Ultra-Low-Power Subthreshold Design. EDCAS has grown up to a team of 15 skilled designers and it has successfully performed 5 tape-outs and has secured >$100k research funding in last 3 years.
Mar 21, 2017
The XBG_1V23LC_V01 is an embedded ultra-low power bandgap reference block which operates with 3.3V power supply. In Standby Mode (PDn = 'L') the power consumption is minimal, VBG will be pulled to ground level. The bandgap IP will be activated with the rising edge of signal PDn (PDn = 'H') and generates an output voltage of 1.23V on pin VBG. The output voltage can be trimmed via signals TR_BG[3:0] in 16 steps. The default combination is 4'b0000.