Ultra Low Power Bandgap Voltage Reference
- AWARD POOL: $ 15000 USD
- DEADLINE: Feb 27, 2017
- ACTIVE SOLVERS: 88
- POSTED: Nov 29, 2016
Design and deliver as a finished IP block an ultra low power bandgap voltage reference. This design challenge emphasizes on both design creativity and execution quality to meet specific target performance requirements. The design should be optimized to minimum power consumption.
Challenge participants will be provided with access to efabless' online design platform with XFAB's XH035 technology. The challenge is open to designers worldwide with a specific outcome of delivering a completed design IP with all its commercially required models, design files and customer documentation.
Schematic Delivery Date Extension
It has come to our attention that simulator-related convergence issues have emerged that are beyond the designers’ control and may affect most or all designs in the Ultra-Low Power Voltage Reference challenge process. We are working on content that will provide designers with guidance on how to avoid failures in your test bench solutions and we are automating these methods in our automatic characterization engine.
As a result, we are moving the delivery date for schematics out one week to January 23, 2017. All subsequent delivery dates will also be pushed out one week. As has been the case, we will not accept any new participants in the challenge after January 15. Thanks for your participation and your support.
The challenge is a first in the semiconductor industry as it is outcome-based with reference to target specifications. There will be no screening of the participants except through a direct automated characterization of the design performance metrics against the required targets.
- Register online at efabless.com
- Review challenge overview and target design specifications
- Should then you choose to enter the challenge, sign the challenge-specific agreement and start!
- Submit a completed schematic to the automated IP parametric comparison vs. targets
- Top 3 target spec-compliant submissions will compete through the finished layout delivery
- Final deliverables will be signed-off through XFAB's tape-out design checks
- Challenge Launch — November 29
- Schematic Submission — January 23, 2017 **
- Schematic Finalists Announced — January 27, 2017
- Final IP Deliverables — February 27, 2017
- Final IP Sign-Off — March 3, 2017
- Winner Announcement — March 6, 2017
efabless developed a complete set of design software including system design, schematic entry, spice simulation, layout editing, DRC, LVS and parasitic extraction. Also a complete RTL-to-GDS digital design flow that includes synthesis, STA, placement and routing.
We also offer a unique, community-oriented verification tool called Automatic Characterization Engine, or ACE. ACE is simulator agnostic and provides automatic verification of a design with reference to control specifications. All new designs must pass ACE certification before entering our efabless marketplace and customers and community can use the ACE tool to ensure a trusted conclusion to a design engagement.
All IP files are abstracted and hidden from everyone except for the designer. If the IP is offered in the efabless marketplace, customers can only access the datasheets and abstracted views for simulation and integration - no schematics or gds data is exposed.
If the IP is not offered in the marketplace, only the IP owner, the designer has access to its information. No other users of the platform are able to access it.