DESIGN CHALLENGE

Ultra Low Power Bandgap Voltage Reference

  • AWARD POOL: $ 15000 USD
  • DEADLINE: Mar 13, 2017
  • ACTIVE SOLVERS: 88
  • POSTED: Nov 29, 2016

Design and deliver as a finished IP block an ultra low power bandgap voltage reference. This design challenge emphasizes on both design creativity and execution quality to meet specific target performance requirements. The design should be optimized to minimum power consumption.

Challenge participants will be provided with access to efabless' online design platform with XFAB's XH035 technology. The challenge is open to designers worldwide with a specific outcome of delivering a completed design IP with all its commercially required models, design files and customer documentation.

Challenge Completed

Thank You To All Participants



WINNERS

1st Place: Rishi Raghav

2nd Place: Arsalan Jawed

3rd Place: Ibrahim Muhammed

6
Passing Customer
Requirements

88
Solvers

26
Countries

Schematic-Only

(In alphabetical order)

Arthur Campos de Oliveira

Mohamed Khairy

Taher Kotb

Participants successfully completed shcematic design phase

Challenge Details

Introduction

Participants are challenged to design and deliver as a finished IP block an ultra low power bandgap voltage reference in XFAB's XH035 process technology. The deliverables should include schematic, behavioral, layout and physical design views as well as full customer documentation. Challenge participants will have access to process PDK and design software through efabless' all-online community platform.

The challenge is a first in the semiconductor industry as it is outcome-based with reference to target specifications. There will be no screening of the participants except through a direct automated characterization of the design performance metrics against the required targets.

General Outline

  • Register online at efabless.com
  • Review challenge overview and target design specifications
  • Should then you choose to enter the challenge, sign the challenge-specific agreement and start!
  • Submit a completed schematic to the automated IP parametric comparison vs. targets
  • Top 3 target spec-compliant submissions will compete through the finished layout delivery
  • Final deliverables will be signed-off through XFAB's tape-out design checks

Key Milestones

  • Challenge Launch — November 29
  • Schematic Submission — January 23, 2017 **
  • Schematic Finalists Announced — January 27, 2017
  • Final IP Deliverables — March 13, 2017
  • Final IP Sign-Off — March 13, 2017
  • Winner Announcement — March 17, 2017
** Access to layout design capabilities is available to challenge participants on December 15th, 2016.

Challenge Awards

1st PLACE  $7,000
2nd PLACE  $5,000
3rd PLACE  $3,000

FAQ

efabless developed a complete set of design software including system design, schematic entry, spice simulation, layout editing, DRC, LVS and parasitic extraction. Also a complete RTL-to-GDS digital design flow that includes synthesis, STA, placement and routing.

We also offer a unique, community-oriented verification tool called Automatic Characterization Engine, or ACE. ACE is simulator agnostic and provides automatic verification of a design with reference to control specifications. All new designs must pass ACE certification before entering our efabless marketplace and customers and community can use the ACE tool to ensure a trusted conclusion to a design engagement.

The PDK (Process Design Kit) name is EFXH035A. It represents the most basic process option set for the X-Fab XH035 0.35um foundry process. The base process option is called "MOS" by X-Fab, and contains only the most basic low-voltage (3.3V) MOS transitors and an assortment of resistors, bipolar transistors, diodes, and metal-sandwich capacitors. Information about the XH035 process options is publicly available on the X-Fab website.
Community members retain the rights to IP created on the system under the Technology Licensing Agreement. However, the IP is maintained on our system and is not available for downloading from the system. This is necessary to enable the ability to design with foundry PDK’s without requiring NDA’s.

All IP files are abstracted and hidden from everyone except for the designer. If the IP is offered in the efabless marketplace, customers can only access the datasheets and abstracted views for simulation and integration - no schematics or gds data is exposed.

If the IP is not offered in the marketplace, only the IP owner, the designer has access to its information. No other users of the platform are able to access it.